Controlled Transition Density Based Power Constrained Scan - BIST with Reduced Test Time

In recent years, circuit size has increased due to scaling down of technology. Controlling power dissipation in these large circuits during test sessions is one of the major concerns in VLSI testing. In general power dissipation of a system in test mode is higher than the normal mode. This extra power can cause problems such as instantaneous power surge that causes circuit damage, formation of hot spots, difficulty in performance verification and reduction of system lifetime and product yield. The reason behind the high power dissipation during test is because unlike normal mode operation of the system correlation between consecutive test patterns does not exist in test mode. This is particularly true in case of Built-In-Self-Test (BIST) and scan -Based BIST, two popular DFT methodologies. To increase the correlation between consecutive vectors during testing, several techniques have been proposed for creating low transition density in the pattern sets and thus control the power dissipation. However, this in turn increases the test application time as the test has to run for longer test sessions to reach sufficient fault coverage. Increase in test time is undesirable as testing cost of a chip is directly related to the time it takes to test the chip. This research aims to provide a common way to deal with both the problems by optimizing test lengths for power constraint scan BIST circuits and reduce required test application time. We first show that test application time can be reduced in a power constrained test set up based on the transition density in the vector sets for the designs which contained multiple scan chains and the power dissipation can be controlled through adapting the scan clock dynamically ensuring that the test process does not cross the power budget. Having a method of speeding up test time for applying test in a power constrained set up; we next analyze how reduction in transition density in vectors affects the fault coverage of a circuit